Chief Engineer, Prototype System Integration and Experimentation

ABOUT NEUROPHOS

The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A https://www.neurophos.com/110m-raise led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!

Location: Austin, TX

Reports To: Chief Technology Officer

FLSA Status: Exempt

POSITION OVERVIEW

We are seeking an exceptional Chief Engineer to own the technical execution of our first fully integrated prototype system. This system spans optical sources, electro-optic modulation, high-speed mixed-signal electronics, free-space optics, a programmable photonic compute element, and the firmware and host software that drive them. A mix of internal teams and external design partners develops each subsystem, and the prototype works only if all of them agree—numerically, electrically, optically, and mechanically—at every interface.

You will be the single technical authority who holds that agreement together. You will own the end-to-end system performance budget, maintain the architecture and interface definitions that all subsystems are built against, scrutinize the designs delivered by internal teams and vendors alike, and drive integration and bring-up in the laboratory. This is a hands-on engineering leadership role, not a program-management role: you will be expected to read a schematic and question a component choice, recompute a budget line and challenge a vendor's assumption, and trace a bring-up anomaly from a measured waveform back to the architectural decision that caused it.

Critically, the first successful demonstration marks the beginning of this role, not its end. The prototype is intended to live on as the company's permanent experimental platform for optical computing—the instrument on which we quantify how individual optical and electrical impairments propagate into end-to-end computational accuracy, and on which we prototype and evaluate alternative mathematical encodings of the core compute operation before committing them to silicon. You will own that platform for its full life: keeping it instrumented, reconfigurable, and trustworthy as a measurement reference, designing and running the experimental campaigns that answer the architecture questions for the next product generation, and ensuring that what we learn on the bench feeds directly into system models and design decisions.

If you have deep multi-disciplinary hardware intuition, the systems-engineering discipline to keep a complex program coherent, the technical credibility to hold both internal teams and external suppliers to a specification, and the experimental rigor to turn a laboratory system into a source of durable physical insight, this role will let you define whether a first-of-its-kind computing platform works—and what comes after it.

PRIMARY RESPONSIBILITIES

• System Performance Budget Ownership: Own, maintain, and defend the end-to-end system performance budget that flows top-level accuracy, signal-to-noise, and bandwidth requirements down into allocations for every subsystem. Keep the budget synchronized with the as-designed and as-measured hardware, identify the dominant performance-limiting elements, and drive the trade studies that resolve them.

• Architecture and Interface Control: Define and maintain the system architecture, requirements set, and interface definitions that every subsystem and supplier designs against. Ensure that electrical, optical, mechanical, thermal, and data interfaces are unambiguously specified, mutually consistent, and traceable to system-level requirements. Adjudicate interface conflicts and control changes as the design evolves.

• Technical Oversight of Suppliers and Design Partners: Serve as the technical counterpart to external design houses and component vendors. Review delivered schematics, layouts, bills of materials, component selections, and analysis packages; verify they meet specifications and stay within the system budget. Lead design reviews, drive resolution of findings, and recommend acceptance or rejection of deliverables.

• Hardware Design Review: Critically evaluate mixed-signal and high-speed electronic designs—drive and termination networks, data converter interfaces, transimpedance and amplification chains, power distribution, grounding, and signal integrity—as well as optical and opto-mechanical designs, for correctness, manufacturability, and margin. Identify errors and risks before they reach fabrication.

• Hardware–Software Alignment: Ensure firmware and host software meet hardware requirements and system-level use cases. Review control and data paths, register maps, timing and sequencing, calibration hooks, and test interfaces; hold the software effort accountable to the same specification and schedule discipline as the hardware.

• Integration, Bring-Up, and Validation: Plan and lead the integration sequence, define acceptance criteria at every subassembly boundary, and drive labo